1. Field of this Invention
This disclosure relates to semiconductor memory devices, and more particularly, to a nonvolatile semiconductor memory device with scalable two transistor memory (STTM) cells.
2. Description of the Related Art
Compared to other memory devices such as SRAM semiconductor devices, DRAM semiconductor devices have an advantage of being able to achieve a higher integration density. But DRAM semiconductor devices cannot maintain a stored charge, as required by scaling, due to leakage current from memory cells, internal noise, and soft errors caused by incident alpha particles. Therefore, the memory cells of such devices require constant refreshing in order to maintain stored data. Thus, power consumption is large even in stand-by mode.
ON the other hand, flash memory devices, or EEPROM devices, have a merit in that there is no need to refresh the memory cells in order to maintain data stored in the memory cells. However, a primary drawback of flash memory devices is that it is difficult to improve its relatively slow access time because it takes a relatively long time to program the memory cells. Moreover, a high voltage is necessary to program (write) or erase memory cells of flash memory devices. The high electric field applied during erase/write cycles degrades the SiO2 tunneling barrier to the floating gate over a predetermined number (typically about 105) of erase/write cycles and, as a result, limits the operational life of the memory device. Thus, there is a need for a novel memory cell device that combines the advantages of DRAM and flash memory. In other words, there is a need for a semiconductor memory device having memory cells that allow scalable memory charge relative to cell density of the device long-term retention, low voltage, high speed, and highly reliable operational characteristics. One such novel memory cell, which can be named as a Scalable Two-Transistor Memory cell, has been proposed by Nazato et al. (refer to IEDM 97, pp. 179–182 and U.S. Pat. No 5,952,692). Nazato et al. referred to their device as a Planar Localized Electron Device Memory (PLEDM) cell. This memory cell has non-volatile, high-speed, very low-power dissipation, and high cell density characteristics. It also has an isolated memory node, which provides immunity against soft errors, and a gain property, which provides a large S/N ratio. It is a quantum tunneling device that works at room temperature with no hot carrier degradation effects, and can be fabricated by exsiting silicon processing technology. Using the STTM cell, the following invention discloses an improved cell array structure so that operation speed is increased.